建筑师Labs目标Two-week芯片设计循环AI-Driven核查

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Home » IC Design » Architect Labs Targets Two-week Chip Design Cycle with AI-Driven Verification Startup combines AI-based design and verification with internal tools to accelerate complex ASIC development from concept to silicon. Architect Labs is building a platform that lets “anybody” design a custom chip, co-founder Ebrahim Hussain told EE Times in an exclusive interview. Supporting that claim, the startup company has built its prototype Redwood chip on an FPGA in record time. “Redwood is the first demonstration that is saying this flow works,” Hussain said. “We can actually take something from idea to at least a proof-of-concept. I don’t think you can get any quicker than two weeks.” That speed includes success on the first batch of test chips from a foundry, known as “A0” silicon. Architect Labs has been using TSMC’s wafer shuttle service that allows multiple chip designs to share a single mask set and production run. “It’s getting very difficult to build complex A0 silicon on the first shot,” Hussain noted. “We want to help chip companies make it faster but [also] make their development higher quality. The end goal is that A0 goes into full production for our partners.” Hussain, now 20, skipped high school to study engineering physics at the University of British Columbia before working briefly as a chip designer for Apple and Tesla and joining Stanford University in 2025 as a visiting researcher. He started Architect Labs in July 2025 with co-founder Aaditya Subedi, 19, who today leads a team of 25 people engaged in machine learning, hardware and software engineering, including chip veterans with 20 to 30 years of experience per person. “I worked for Apple, I worked for Tesla,” Hussain said. “I was on the architecture team and saw how long these cycles really were. It felt like AI would have a big impact on the chip design cycle, but at the same time, it felt like the approach that many people were taking in terms of using AI was not really that potent, it didn’t really feel like it could change much.” Architect Labs said its technology lets people provide inputs to an AI system that can take over the design and verification of a chip. “It can test the firmware stack, how the software will interact with the chip,” Hussain said. “It’s very orthogonal to how the traditional verification flow is. Redwood is our first test that is showing this verification technique scales, and we can build complex chips with it.” The company has built internal blocks and intellectual property for Redwood, which Architect Labs uses as its own training data to recursively improve models. The company used Anthropic’s Claude Opus 4.6 as a primary frontier benchmark for the development of Architect Labs’ models . “We’ll be releasing a future post about how we’ve gotten our models to actually beat whatever the frontier is providing, which is exciting,” Hussain said. OpenAI’s Jalapeño and Amazon’s Trainium demonstrate that more people can create a high-performance chip that’s as good as any inference silicon, Steve Jang, founder of Kindred Ventures and an investor in Architect Labs, told EE Times. “There’s a serious opportunity to open up this market,” Jang added. “Architect Labs has an opportunity to be analogous the way Claude Code is to software.” In Architect Labs’ case, the company is using AI to slash chip design time. One notion is that even with a reduced design team, lead time, and capital needs, a project can get halfway to a “productionized” chip in a few weeks, Jang said. “That’s really cool,” he noted. “Because then you’re making go/no-go decisions with capex and time and resources, having something that you’ve at least been able to test on an FPGA and then run something better than simulations. It would take you a year to two, three years to do that before.” Hussain didn’t name customers but said Architect Labs is working with partners to design “some of the most complex ASICs in the world, full-reticle networking