TSMC OIP:芯片工业增长吹嘘过去的预测

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Aggressive prediction of $1T by 2030 was $700B too low. Here’s why. TSMC presented company and semiconductor industry updates at its Open Innovation Partners North America Technology Symposium last week. In January 2024, TSMC’s Kevin Zhang presented the slide below (see figure 1) for the Semiconductor Industry Outlook at ISSCC. It projected what then seemed like a bold forecast for worldwide semiconductor revenue to reach ~$1T by 2030. Fig. 1: 2024 semiconductor industry outlook forecast. Source: TSMC At this year’s OIC, TSMC North America CEO Sajiv Dalal said the Semiconductor Industry will hit ~1.7T by end of year, with > $1T for AI alone. Dalal’s forecast is also in line with Gartner’s forecast of ~$1.6T for the industry in 2026. This is an incredible leap on top of what originally seemed like an ambitious forecast. The surge in AI semiconductor spending has been accelerating at a ferocious pace. The slide shown above in Figure 2. shows revenue layered on top of TSMC technology and product milestones. The AI era portion highlights the current accelerated growth in revenue. TSMC’s recent revenue numbers, shown in Table 1, show a 53.3% year-over-year increase and, for comparable January-to-August numbers for 2025 and 2026, a whopping 39.3% increase. Figure 3 shows projected growth across HPC/mobile, auto and IoT segments. Li-Pen Yuan, vice president of business development at TSMC, said the number of new tape-outs (NTOs) had increased by 4× as measured by the second year of a new technology across the N5, N3 and N2 technologies. This is a massive acceleration in the number of new designs targeted for the N2 technology, which continues beyond N3’s increased new design rate. The AI build-out increasingly makes new demands on compute, memory density, and power, as is shown in the projections for industry in figure 4. L.C. Lu, TSMC senior fellow and vice president for design and technology platforms, said inference token usage has grown 500× over the past three years and that inference is becoming the growth driver for AI. Lu noted that power scaling extends Moore’s Law. For TSMC’s A14 Nanoflex, the cell height goes to 1.5× (vs. 2× for previous nodes), with a14% improvement in speed and 23% reduction in power versus N2P. Figure 5, above, shows HPC cell power efficiency improvements of 2.3× when going from N3P to A12 SPR. For memory, Lu presented a figure of merit based on the number of transistors × speed@power. (#Trans × speed@Power). This benchmark will increase by 87× in 2029, based on predicted improvements from technology advancements. In five years, bandwidths for HBM will increase 34×, 3D DRAM 115×, and SRAM by 830×. The 2029 forecasts for energy/bit are SRAM 0.32pJ/bit, 3DDRAM 1pj/Bit, and HBM 2.5pJ/bit. In an article covering the 2024 TSMC OIP, TSMC’s Plan For Closing The Communication Gap , the introduction of TSMC’s COUPE was discussed as an important milestone for TSMC to enable energy-efficient high-speed communication as serial data rates jump to 224G and 448G. TSMC-COUPE addresses the need for higher bandwidth with lower energy per bit. Figure 6 shows the future roadmap for TSMC-COUPE, including serial data rate increases in gigabits per second (Gbps). The ability to incorporate multiple wavelengths per fiber increases the overall bandwidth capacity of the fiber, as each wavelength is a carrier of high-speed data. AI is now acting in a positive feedback environment, where advances in AI are leading to new tools and productivity in the development of new AI technologies. Greg Dix, vice president of engineering for Broadcom’s ASIC Products Division, said from project kick-off to tape-out of OpenAI’s Jalapeno custom AI ASIC was accomplished in just nine months. Dix noted that, in his view, the SoC era is ending and SiP is accelerating. In new partnerships, Yuan noted that TSMC recently added imec as a partner, and IC-Link by imec received a partner of the year award following IC-Link’s integration into th